
`include "common_header.verilog"

//  *************************************************************************
//  File : encode64.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited.
//  Copyright (c) 2008 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Muhammad Anisur Rahman
//  info@morethanip.com
//  *************************************************************************
//  Description : 10G/100G Base-R PCS Transmit: Block Encoder Structure
//                Unregistered output!
//  Version     : $Id: encode64.v,v 1.4 2014/11/27 17:02:49 dk Exp $
//  *************************************************************************

module encode64 (

        reset,
        clk,
        clk_ena,
        en_gen_pat,
        tx_d_out,
        tx_c_out,

`ifdef MTIP_DEBUG_BUSES
        encode_err,
`endif
        data_out,
        data_type
`ifdef MTIPPCS_EEE_ENA
                ,        
        t_type_li
`endif        
        
        );

input                   reset;                  //  asynch reset
input                   clk;                    //  system clock
input                   clk_ena;                //  clock enable
input                   en_gen_pat;             //  enable test pattern generator
input   [63:0]          tx_d_out;               //  data from XL/CGMII bus
input   [7:0]           tx_c_out;               //  control lane from XL/CGMII bus
`ifdef MTIP_DEBUG_BUSES
output                  encode_err;             //  encode can not be done
`endif
output  [63:0]          data_out;               //  data encoded 64B/66B format
output  [1:0]           data_type;              //  data block type (10: data / 01: control)
`ifdef MTIPPCS_EEE_ENA
output                  t_type_li;              //  LI Block type received
`endif 
`ifdef MTIP_DEBUG_BUSES
wire    		encode_err;
`endif
wire    [63:0]          data_out; 
wire    [1:0]           data_type; 

`ifdef MTIPPCS_EEE_ENA
wire                    t_type_li;      //  LI Block type received 
`endif 

wire 			convert2clause49;		// convert the ordered set fram clause 82 to clause 49
wire [63:0] 		tx_d_out_int;
wire [7:0] 		tx_c_out_int;
wire                    en_gen_pat_s;	// CDC enable pattern
// from classification for pipeline
wire    [63:0] 		data_s;        //  Data out
wire    [3:0]           block_0;    //  Class block
wire                    c_0; //  C Block type received
wire                    s_0; //  S Block type received
wire                    t_0; //  T Block type received
wire                    d_0; //  D Block type received
wire                    e_0; //  E Block type received
`ifdef MTIPPCS_EEE_ENA
wire                    li_0; 
`endif

wire                    encode_0; //  encode can be done


mtip_dffvec #(1) U_PIPGENPAT (
          .reset(reset),
          .clk(clk),
          .i(en_gen_pat),
          .o(en_gen_pat_s));


// convert the ordered set from clause82 to clause49
assign  convert2clause49 = 	((tx_d_out[7:0]==8'h 9C || tx_d_out[7:0]==8'h 5C) && tx_d_out[63:32]==32'h 0 && tx_c_out[7:0] == 8'h 01);

assign tx_d_out_int[63:32] 	= (convert2clause49==1'b 1 || en_gen_pat_s==1'b 1) ? 32'h 07070707 : tx_d_out[63:32];
assign tx_d_out_int[31:0]  	= (en_gen_pat_s==1'b 1) ? 32'h 07070707 : tx_d_out[31:0]; 				// force IDLE as pattern TX

assign tx_c_out_int[7:4] 	= (convert2clause49==1'b 1 || en_gen_pat_s==1'b 1) ? 4'b 1111 : tx_c_out[7:4];
assign tx_c_out_int[3:0] 	= (en_gen_pat_s==1'b 1) ? 4'b 1111 : tx_c_out[3:0];					// force IDLE as pattern TX


// Block type detection (10GBase-R)
tx_block_type_10l U_TXTYPE(

   .reset(reset),
   .clk(clk),
   .clk_ena(clk_ena),
   .tx_d_out(tx_d_out_int[63:0]),
   .tx_c_out(tx_c_out_int[7:0]),
   .data_out(data_s),
   .class_block(block_0),
   .t_type_c(c_0),
   .t_type_s(s_0),
   .t_type_t(t_0),
   .t_type_d(d_0),
   .t_type_e(e_0),
    `ifdef MTIPPCS_EEE_ENA
   .t_type_li(li_0),
   `endif   
   .loc_fault(),
   .rem_fault ());


// Block check statemachine
tx_block_check_10l U_BLOCKCHECK(
   .reset(reset),
   .sw_reset(1'b 0),
   .clk(clk),
   .clk_ena(clk_ena),
    `ifdef MTIPPCS_EEE_ENA
   .t_type_li(li_0), 
   `endif     
   .t_type_c(c_0),
   .t_type_s(s_0),
   .t_type_t(t_0),
   .t_type_d(d_0),
   .t_type_e(e_0),
   .t_type_val(1'b 1),
   .encode(encode_0),
   .local_fault(),
   .error());

`ifdef MTIP_DEBUG_BUSES
assign  encode_err = !encode_0;
`endif


// Encode 64/66 (10GBase-R)
tx_block_encode_10l U_ENCODE(
   .reset(reset),
   .sw_reset(1'b 0),
   .clk(clk),
   .clk_ena(clk_ena),
   .data_in(data_s),
   .class_block(block_0),
   .encode(encode_0),
   .data_out(data_out),
   .data_type(data_type));





`ifdef MTIPPCS_EEE_ENA

mtip_dffvec_ena #(1) U_PIPLPI(
   .reset(reset),
   .clk(clk),
   .ena(clk_ena),
   .i(li_0),
   .o(t_type_li));

`endif 


endmodule // module encode64

